1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a memory device of an electrically programmable read-only memory (EPROM) including a nonvolatile semiconductor memory element.
2. Description of the Prior Art
There have been disclosed nonvolatile semiconductor memory devices such as one employing as memory cells nonvolatile semiconductor memory elements each having a floating gate, for example, in the Japanese Patent Laid-Open Publication No. 154692/1984 and the Japanese Patent Publication No. 38675/1984.
The memory element described in the first article is identical in the configuration thereof to one schematically shown in FIGS. 7A and 7B. That is, these elements have the planar pattern shown in FIG. 7A and a cross sectional form shown in FIG. 7B and taken along VIIB--VIIB of FIG. 7A. As shown in those figures, the memory element is configured such that, for example, a source region 2 and a drain region 3 each of an n.sup.+ -type region are formed on a surface area of a p-type substrate 1. A floating gate 6 is disposed via an insulation layer 5 over a channel region 4 between the source and drain regions 2 and 3, and a control gate 7 is formed thereover via the insulation layer 5. In the memory element having such a structure, electrons are injected into the floating gate 6 so as to increase a threshold voltage as a metal-oxide-semiconductor, MOS, transistor, thereby electrically writing data therein.
FIG. 8 shows a planar pattern of a memory element array in which memory elements each having the configurations shown in FIGS. 7A and 7B are integrally arranged along vertical and horizontal directions in a matrix form. In this structure, a plurality of rows 17-1, 17-2, etc. are formed so as to extend in parallel to each other along a vertical direction. These row lines or strips 17 are wirings associaed with the control gates 7 and are formed with polycrystalline silicon layers disposed as second layers relative to the substrate 1. Beneath the row lines 17, there are formed floating gates 16-1, 16-2, etc. of polycrystalline silicon layers disposed as first layers. In addition, sandwiched by the respective floating gates 16, there are formed n.sup.+ -type diffusion layers 12-1, 12-2, etc. as source regions 2 of the respective memory elements 15, and n.sup.+ -type diffusion layers 12-1, 13-2, etc. as drain regions 3 thereof. In this structure, the n.sup.+ -type diffusion layer 12 is disposed for each two rows. The n.sup.+ -type diffusion layer 13 is formed for a pair of adjacent memory cells 15 so as to be connected to wirings 18-1, 18-2, etc. disposed as columns extending along a transverse direction in parallel to each other. Incidentally, the memory cell elements 15-1, 1-2, etc. are respectively arranged at intersections between the rows 17 and column wirings 18. In the memory element array, wirings 19-1, etc. are formed to be parallel to the wirings 18 as columns in a regular arrangement, for example, each for eight columns, so as to be connected to the n.sup.+ -type diffusion layer 12.
FIG. 9 shows an equivalent circuit of the memory element array of FIG. 8. The reference numerals in FIG. 9 correspond to those indicated in FIG. 8. In this structure, n.sup.+ -type diffusion layers 12 as common source wirings of the memory elements 15 develop a resistance of about several tens ohms per square micrometer, .mu.m.sup.2 and is hence indicated with a resistor symbol in FIG. 9.
In a case where a programming operation of data is carried out on the memory elements 15, the source wiring 19 common to the memory elements 15 are set to a ground level and a high voltage is applied to one of the rows and to one of the columns. That is, the high voltage is applied across the gate and the source as well as the drain and the source of a memory element 15 located at an intersection between the row and the column to which the high voltage is applied, which causes an avalanche effect in the proximity of the drain 3 of the memory cell 15 such that hot electrons thus produced are injected into the floating gate 6 so as to change the threshold voltage of the memory element 15 as the MOS transistor. In the programming operation, the programming current passing through the memory element 15 reaches several milliamperes. In this situation, if the n.sup.+ -type diffusion layers 12 are associated with a high parasitic resistance, the source potential of the memory element 15 to be programmed by the program current is increased, which leads to a difficulty of the programming operation. To avoid this disadvantage, it is commonly employed that the wiring 18 is disposed each for a plurality of columns, each for eight columns in this particular instance.
Moreover, in Dennis R. Wilson et al. "A 100 ns 150 mW 64 bit ROM" ISSCC 1978, pp. 152-153 and 273, there is proposed a memory arrangement method called shared contact of which a planar pattern is shown in FIG. 10. The longitudinal structure of the memory element is the same as that of the memory element of FIG. 7B. Columns 28-1, 28-2, etc. are wirings to be connected to n.sup.+ -type diffusion layers 23-1, 23-2, etc. forming drains 3 of the respective memory elements 25-1, 25-2, etc. whereas columns 29-1 etc. are wirings to be linked with n.sup.+ -type diffusion layers 22-1, 22-2, etc. configuring sources 2 of the memory elements 25 such that the columns 28 and 29 are alternately arranged in a vertical direction so as to extend in the transversal direction. The memory elements 25 are arranged such that the direction of the channel width thereof is inclined by 45 degrees with respect to the columns. That is, in this figure, the starting point, ending point and intersection of lines constituting a letter " X" are n.sup.+ -type diffusion layers of the drain 3 or the source 2 of the memory elements 25, and these n.sup.+ -type diffusion layers are linked with the columns 28 or 29. Rows 27-1, 27-2, etc. are formed to extend in parallel with each other in the vertical direction. These rows 27 are wirings associated with the control gate 7.
FIG. 11 shows equivalent circuits of the memory elements of FIG. 10. The reference numerals used in FIG. 11 are assigned in association with those of FIG. 10.
In an operation to program a particular memory element 25, as described in the Japanese patent publication No. 38675/1984, all columns 29 linked with the sources 2 of the memory elements 25 are beforehand pulled up via a high-resistance load to a potential of the power supply Vcc such that one of the columns 29 is lowered to the ground level. A high voltage is then applied to either one of two columns 28 adjacent to the column at the ground level. In this situation, by setting one of the rows 27 to a high voltage, the programming operation is achieved on a memory element 25 to which a high voltage is applied across the gate and the source as well as the drain and the source thereof like in the case of the programming of the memory element 15 shown in FIG. 9.
However, in the conventional device of the configuration shown in FIG. 8, a considerable amount of parasitic resistance is developed through the n.sup.+ -type diffusion layer as the source regions of the memory elements; and in order to reduce the resistance, it is necessary to dispose columns of the source regions of the memory elements in the memory element array. In addition, when a thiner line is employed for the elements, the resistance of the n.sup.+ -type diffusion layer becomes higher and hence the ratio of the source columns in the memory elements greatly increases: in consequnce, there arises a problem that the chip area becomes greater.
On the other hand, in this regard, according to the device of the prior art having the configuration of FIG. 10, it is possible to decrease the chip area at least by ten percent. In consequence, the device may be designed in a submicron order. According to the design rule in the submicron area, an electron beam exposure apparatus is required to be adopted to form a pattern. However, in the operation data of the exposure apparatus, there does not exist any data associated with an exact 45-degree scanning operation. For example, when an attempt is made to scan a 45-degree line, a step-wise line is assumed for the 45-degree line, and hence there appears a problem that the finishing precision is lowered in the memory elements located along an inclined line in the device of the constitution of FIG. 10.